There are multiple sources of variations that may affect an integrated circuit, such as process (P) variation, supply voltage (V) variation, and operating temperature (T) variation, often referred to as PVT corners. Each source of variation may affect the entire integrated circuit or part of it. For example, the temperature variation caused by changes in ambient temperature may affect all the transistors and interconnects on an integrated circuit in the same way, while the temperature differences due to the presence of a temperature gradient (e.g., the presence of hot spots) on the integrated circuit may cause different parts of the integrated circuit to operate at different temperatures.
Process variations due to die-to-die and intra-die variations may cause significant differences between the designed and the manufactured functional circuits in nanometer technologies as process tolerances might not scale proportionally with the design dimensions, causing the relative impact of variations to increase with every new technology generation. Precise detection and compensation schemes to mitigate variations and optimize the post-fabrication operating characteristics of a functional circuit to meet its target frequency and power consumption have become useful for yield enhancement and improvement.
Some conventional solutions include designing functional circuits with excessive design margin to deal with process variation and to help ensure the circuit meets its required timing. Other known solutions consist of a sensor circuit determining the extent of a process variation followed by a compensation circuit that alters the operating characteristics of the functional circuit appropriately. As such, the efficiency of the compensation scheme may depend on the accuracy of the detection (sensor) circuit. Some of these schemes are based on monitoring the delay of the critical path of the functional circuit, such as an inverter chain or a replica circuitry. Consequently, either the supply voltage is adjusted or the threshold voltage is modulated by changing the bias voltage applied to the circuit transistors.
The variation of fabrication parameters when designing an integrated circuit (i.e., a functional circuit) is defined as process variation. Process corners represent the extremes of these parameter variations within which the circuit may function correctly. P-channel and n-channel transistors fabricated at these process corners may run slower or faster than specified and at lower or higher temperatures and voltages. Such mismatches between PMOS and NMOS transistors may affect the circuit characteristics. For example in a skewed corner, one transistor (e.g., p-channel) may switch much faster than the other (e.g., n-channel), which causes imbalanced switching which in turn may result in cells failing. In near threshold operation, when a functional circuit operates at a voltage near the threshold voltage of the transistors, the effect of skewed corners may become even more pronounced. As a result, the minimum operating supply voltage for skewed corners is higher than for even corners (for example when both NMOS and PMOS transistors switch faster). Balanced N and P transistors may enable lower circuit operating voltage and power, while providing a higher static noise margin. Any mismatch between these two types of transistors may cause degradation of the noise margin, minimum operating voltage, and also performance and power of the circuit.
In the paper “Vr Balancing and Device Sizing Towards High Yield of Sub-threshold Static Logic Gates” (Y Pu et al, Proc. ISPLED, pp. 355-358, August, 2007) a digital solution for detection of the difference between the PMOS and NMOS transistor mismatches has been proposed.